Conferences

2025

1. H. Shin, J. Kung, "FlexENM: A flexible encrypting-near-memory with refresh-less eDRAM-based multi-mode AES," accepted for publication at Design, Automation and Test in Europe Conference (DATE), March 2025.

2. G. Kang*, D. Park*, H. Lee, S. Jung, J. Park, J. G. Min, Y. Lee, J. Kung, "RISC-V driven orchestration of vector processing units and eFlash compute-in-memory arrays for fast and accurate keyword spotting," accepted for publication at IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), January 2025. *Equally Contributed Authors

2024

1. S. Hwang, S. Lee, D. Park, D. Lee, J. Kung, "SpikedAttention: Training-free and fully spike-driven transformer-to-SNN conversion with winner-oriented spike shift for softmax operation," accepted for publication at the Annual Conference on Neural Information Processing Systems (NeurIPS), December 2024.

2. D.-G. Choi, J. Lee, J. Koo, W. K. Han, D. Park, J. Kung, J. Lee, J.-H. Yoon, "A 65nm 687.5-TOPS/W drive strength-based SRAM compute-in-memory macro with adaptive dynamic range for edge AI applications," accepted for publication at IEEE Asian Solid-State Circuits Conference (A-SSCC), November 2024.

3. J. Koo*, D. Park*, S. Jung, J. Kung, "OPAL: Outlier-preserved microscaling quantization accelerator for generative large language models," IEEE/ACM Design Automation Conference (DAC), June 2024. *Equally Contributed Authors

4. J. Lee, D. Lee, J. Kung, "A ready-to-use RTL generator for systolic tensor arrays and analysis using open-source EDA tools," IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.

5. J. Wie, S. Jung, T. Seol, G. Kim, S. Lee, H. Jang, S. Kim, Y. Shin, J. E. Jang, J. Kung, A. K. George, J. Lee, "A 3.3-to-11V-supply-range 10μW/Ch arbitrary-waveform-capable neural stimulator with output-adaptive-self-bias and supply-tracking schemes in 0.18μm standard CMOS," IEEE Custom Integrated Circuits Conference (CICC), April 2024.

6. J. Kim, S. Oh, J. Kung, Y. Kim, S. Lee, "NDPipe: exploiting near-data processing for scalable inference and continuous training in photo storage," ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2024.

7. S. Jeong, J. Lee, J. Kung, "A full SW-HW demonstration of GEMM accelerators with RISC-V instruction extensions," IEEE/IEIE International Conference on Electronics, Information, and Communication (ICEIC), January 2024.

2023

1. S. Lee*, J. Choi*, S.-H. Noh, J. Koo, J. Kung, “DBPS: dynamic block size and precision scaling for efficient DNN training supported by RISC-V ISA extensions,” ACM/IEEE Design Automation Conference (DAC), July 2023. *Equally Contributed Authors

2. B. Shin, S. Park, J. Kung, "Improving hardware efficiency of a sparse training accelerator by restructuring a reduction network," IEEE Interregional NEWCAS conference (NEWCAS), June 2023.

3. T. Seol, S. Lee, G. Kim, S. Kim, E. Kim, S. Baik, J. Kung, J.-W. Choi, A. K. George, J. Lee, "A 1V 136.6dB-DR 4kHz-BW ΔΣ current-to-digital converter with a truncation-noise-shaped baseline-servo-loop in 0.18um CMOS," IEEE International Solid-State Circuits Conference (ISSCC), February 2023.

2022

1. S.-H. Noh, J. Park, D. Park, J. Koo, J. Choi, J. Kung, “LightNorm: area and energy-efficient batch normalization hardware for on-device DNN training,” IEEE International Conference on Computer Design (ICCD), October 2022.

2. S. Jung, J. Lee, H. Noh, J.-H. Yoon, J. Kung, “DualPIM: a dual-precision and low-power CNN inference engine using SRAM- and eDRAM-based processing-in-memory arrays,” IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), June 2022.

2021

1. M. Bodenham, J. Kung, “On the extensive exploration of transformer-based language models for memory and latency bounded edge devices,” Workshop on ROAD4NN at IEEE/ACM Design Automation Conference (DAC), December 2021.

2. D. Park, S. Im, K.-W. Kwon, J. Kung, “ZeBRA: precisely destroying neural networks with zero-data based repeated bit flip attack,” British Machine Vision Conference (BMVC), November 2021.

3. S. Hwang, J. Lee, J. Kung, “Adaptive input-to-neuron interlink development in training of spike-based liquid state machines,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.

2019

1. S. Jung, J. Kung, “Noise tolerance of an energy-scalable deep learning model with two extreme bit-precisions,” IEEE International SoC Design Conference (ISOCC), October 2019. (Cadence Award Winner)

2. J. Joe, J. Kung, S. Lee, Y. Lee, “Similarity-based LSTM architecture for energy-efficient edge-level speech recognition,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2019.

3. S. Jung, S. Moon, Y. Lee, J. Kung, “MixNet: an energy-scalable and computationally lightweight deep learning accelerator,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2019.

4. J. Kung, J. Park, S. Park, J.-J. Kim, “Peregrine: a flexible hardware accelerator for LSTM with limited synaptic connection patterns,” IEEE/ACM Design Automation Conference (DAC), June 2019.

2018

1. S. Mukhopadhyay, M. Wolf, M. F. Amir, E. Gebahrdt, J. H. Ko, J. Kung, B. A. Musassar, “The CAMEL approach to stacked sensor smart cameras” Design, Automation and Test in Europe (DATE), March 2018.

2. J. Park, J. Kung, W. Yi, J.-J. Kim, “Maximizing system performance by balancing computation loads in LSTM accelerators” Design, Automation and Test in Europe (DATE), March 2018.

2017

1. J. H. Ko, Y. Long, M. F. Amir, D. Kim, J. Kung, T. Na, A. R. Trivedi, S. Mukhopadhyay, “Energy-efficient neural image processing for internet-of-things edge devices” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2017.

2. J. Kung, Y. Long, D. Kim, S. Mukhopadhyay, “A programmable hardware accelerator for simulating dynamical systems” IEEE International Symposium on Computer Architecture (ISCA), June 2017. 

3. T. Na, J. H. Ko, J. Kung, S. Mukhopadhyay, “On-chip training of recurrent neural networks with limited numerical precision” IEEE International Joint Conference on Neural Network (IJCNN), May 2017.

4. J. Kung, Y. Long, D. Kim, S. Mukhopadhyay, “An energy-efficient physical platform for solving differential equations” 42th Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2017.

5. J. H. Ko, T. Na, D. Kim, J. Kung, S. Mukhopadhyay, “Adaptive weight compression for memory-efficient neural networks” Design, Automation and Test in Europe (DATE), March 2017.

2011-2016

1. J. Kung, D. Kim, S. Mukhopadhyay, “Dynamic approximation with feedback control for energy-efficient recurrent neural network hardware” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2016.

2. M. F. Amir, D. Kim, J. Kung, D. Lie, S. Yalamanchili, S. Mukhopadhyay, “NeuroSensor: A 3D image sensor with integrated neural accelerator” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016. (Best Student Paper Award)

3. Y. Long, E. M. Jung, J. Kung, S. Mukhopadhyay, “ReRAM crossbar based recurrent neural network for human activity detection” IEEE International Joint Conference on Neural Network (IJCNN), July 2016.

4. D. Kim, J. Kung, S. Chai, S. Yalamanchili, S. Mukhopadhyay, “Neurocube: a programmable digital neuromorphic architecture with high-density 3D memory” ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2016.

5. D. Kim, J. Kung, S. Chai, S. Yalamanchili, S. Mukhopadhyay, “Neurocube: a scalable, efficient platform for neuro-inspired computing” 41st Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2016.

6. J. Kung, D. Kim, S. Mukhopadhyay, “A power-aware digital feedforward neural network platform with backpropagation driven approximate synapses” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), July 2015.

7. J. Kung, M. Cho, S. Yalamanchili, S. Mukhopadhyay, “On-line real-time temperature and power estimation of an IC using time-domain thermal Filters” IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS), October 2013.

8. J. Kung, I. Han, S. S. Sapatnekar, Y. Shin, “Thermal signature: a simple yet accurate thermal index for floorplan optimization” ACM/EDAC/IEEE Design Automation Conference (DAC), June 2011.

9. J. Kung, Y. Shin, “Compact thermal models: assessment and pitfalls” IEEE International SoC Design Conference (ISOCC), November 2011.

10. S. Paik, J. Kung, Y. Shin, “Exploring the opportunity of optimizing sequencing elements in ASIC designs” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011.